This invention relates to integrated circuit structures and, more particularly, to metal-oxide-semiconductor (MOS) integrated circuit transistor devices which include Schottky-barrier (SB) source and drain contacts and to methods for making such devices.
It is known that utilizing SB contacts for the source and drain of a conventional p-channel or n-channel enhancement-mode MOS transistor device results in performance and fabrication advantages. It is also now known that the incorporation of such contacts in a standard integrated circuit employing complementary metal-oxide-semiconductor (CMOS) transistor devices in the same substrate chip is highly advantageous. As set forth in U.S. Pat. No. 4,300,152, issued to M. P. Lepselter, the inclusion of SB source and drain contacts in at least one of the complementary pair of MOS devices in a CMOS structure results in a meritorious arrangement that is incapable of latchup at any device packing density.
But, particularly for some low-voltage short-channel MOS and CMOS devices of practical importance, it has recently been determined that further improvements in the operating characteristics of SB-MOS and SB-CMOS structures as heretofore proposed would be advantageous. In particular, it has been realized by applicants that improvements in the current sourcing capabilities and in the leakage characteristics of such devices are desirable. Accordingly, considerable effort has recently been directed at trying to improve these properties of the devices. It was recognized that this effort, if successful, could make the device attractive contenders for large-scale commerical use in important applications such as random access memories and microprocessors.